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data sheet ics845252aki revision a september 30, 2009 1 ?2009 integrated device technology, inc. femtoclock ? crystal-to-cml clock generator ICS845252I general description the ICS845252I is a 3.3v/2.5v cml clock generator designed for ethernet applications. the device synthesizes either a 50mhz, 62.5mhz, 100mhz, 125mhz, 156.25mhz, 250mhz or 312.5mhz clock signal with excellent phase jitter performance. the clock signal is distributed to two low-skew differential cml outputs. the device is suitable for driving the reference clocks of ethernet phys. the device supports 3.3v and 2.5v voltage supply and is packaged in a small, lead-free (rohs 6) 32-lead vfqfn package. the extended temperature range supports telecommunication, wireless infrastructure and networking end equipment requirements. the device is a mem ber of the hiperclocks? family of high performance clock solutions from idt. features ? clock generation of: 50mhz, 62.5mhz, 100mhz, 125mhz, 156.25mhz, 250mhz and 312.5mhz ? two differential cml clock output pairs ? crystal interface designed for 25mhz, 18pf parallel resonant crystal ? rms phase jitter @ 125mhz, using a 25mhz crystal (1.875mhz ? 20mhz): 4 00fs (typical), 3.3v offset noise power 100hz.................... -102.4 dbc/hz 1khz.................... -119.4 dbc/hz 10khz................... -124.8 dbc/hz 100khz................... -125.7 dbc/hz ? lvcmos interface levels for the control inputs ? full 3.3v and 2.5v supply voltage ? available in lead-free (rohs 6) 32 vfqfn package ? -40c to 85c ambient operating temperature hiperclocks? ic s block diagram vco 490-680 mhz q0 nq0 q1 nq1 osc xtal_in xtal_out ref_clk ref_sel fbsel nbypass fsel1:0 noe phase detector 20, 25 (default) 2 (default), 4, 5, 10 0 1 f ref 0 1 pulldown pulldown pulldown pullup pulldown, pulldown pulldown pin assignment ICS845252I 32 lead vfqfn 5.0mm x 5.0mm x 0.925mm package body k package top view 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 nq0 q0 v dd noe nc nc nc nc nc nc ref_sel fsel1 fsel0 nc v dd nc nc v dda nbypass ref_clk gnd xtal_out xtal_in nc nc nc gnd q1 nq1 fbsel nc nc
ics845252aki revision a september 30, 2009 2 ?2009 integr ated device technology, inc. ICS845252I data sheet femtoclock? crystal-to-cml clock generator table 1. pin descriptions note: pulldown and pullup refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2 nq0, q0 output differential clock output pa ir. cml interface levels. 3, 18 v dd power core supply pins. 4noeinputpulldown output enable pin. see table 3e for function. lvcmos/lvttl interface levels. 5, 6, 7, 8, 9, 16, 17, 19, 23, 24, 25, 30, 31, 32 nc unused do not connect. 10 v dda power analog supply pin. 11 nbypass input pullup pll bypass pin. see table 3d for function. lvcmos/lvttl interface levels. 12 ref_clk input pulldown single-ended reference clock input. lvcmos/lvttl interface levels. 13, 29 gnd power power supply ground. 14, 15 xtal_out, xtal_in input crystal oscillator interface. xtal_in is the input, xtal_out is the output. 20, 21 fsel0, fsel1 input pulldown output frequency divider select enabl e pins. see table 3c for function. lvcmos/lvttl interface levels. 22 ref_sel input pulldown pll reference clock select pin. see table 3a for function. lvcmos/lvttl interface levels. 26 fbsel input pulldown pll feedback divider select pin. see table 3b for function. lvcmos/lvttl interface levels. 27, 28 nq1, q1 output differential clock output pa ir. cml interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4pf r pulldown input pulldown resistor 51 k ? r pullup input pullup resistor 51 k ?
ics845252aki revision a september 30, 2009 3 ?2009 integr ated device technology, inc. ICS845252I data sheet femtoclock? crystal-to-cml clock generator function tables table 3a. pll reference cl ock select function table note: ref_sel is an asynchronous control. table 3b. pll feedback select function table note: fbsel is an asynchronous control. table 3c. output divider select function table note: fsel[1:0] are a synchronous controls. table 3d. pll nbypass function table note: nbypass is an asynchronous control. table 3e. output enable function table note: noe is an asynchronous control. input operation ref_sel 0 (default) the crystal interface is the selected. 1 the ref_clk input is the selected. input operation fbsel 0 (default) f vco = f ref * 25 1f vco = f ref * 20 input operation output frequency f out with f ref = 25mhz fsel1 fsel0 fbsel = 0 fbsel = 1 0 (default) 0 (default) f out = f vco 2 312.5mhz 250mhz 01f out = f vco 4 156.25mhz 125mhz 10f out = f vco 5 125mhz 100mhz 11f out = f vco 10 62.5mhz 50mhz input operation nbypass 0 pll is bypassed. the reference frequency f ref is divided by the selected output divider. ac specifications do not apply in pll bypass mode. 1 (default) pll is enabled. the reference frequency f ref is multiplied by the selected feedback divider and then divided by the selected output divider. input operation noe 0 (default) outputs enabled. 1 outputs disabled (high-impedance).
ics845252aki revision a september 30, 2009 4 ?2009 integr ated device technology, inc. ICS845252I data sheet femtoclock? crystal-to-cml clock generator absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v5%, t a = -40c to 85c table 4b. power supply dc characteristics, v dd = 2.5v5%, t a = -40c to 85c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuous current surge current 10ma 15ma package thermal impedance, ja 43.4c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage v dd ? 0.12 3.3 v dd v i dd power supply current 88 ma i dda analog supply current 12 ma symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 2.375 2.5 2.625 v v dda analog supply voltage v dd ? 0.11 2.5 v dd v i dd power supply current 84 ma i dda analog supply current 11 ma
ics845252aki revision a september 30, 2009 5 ?2009 integr ated device technology, inc. ICS845252I data sheet femtoclock? crystal-to-cml clock generator table 4c. lvcmos/lvttl input dc characteristics, v dd = 3.3v5% or 2.5v5%, t a = -40c to 85c table 4d. cml dc characteristics, v dd = 3.3v5% or 2.5v5%, t a = -40c to 85c table 5. crystal characteristics symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v dd = 3.3v 2v dd + 0.3 v v dd = 2.5v 1.7 v dd + 0.3 v v il input low voltage v dd = 3.3v -0.3 0.8 v v dd = 2.5v -0.3 0.7 v i ih input high current fbsel, noe, fsel[1:0], ref_sel, ref_clk v dd = v in = 3.465v 150 a nbypass v dd = v in = 3.465v 5 a i il input low current fbsel, noe, fsel[1:0], ref_sel, ref_clk v dd = 3.465v or 2.625v, v in = 0v -5 a nbypass v dd = 3.465v or 2.625v, v in = 0v -150 a symbol parameter test conditions minimum typical maximum units v oh output high voltage v dd - 0.02 v dd - 0.01 v dd v v out output voltage swing 325 400 600 mv v diff_out differential output voltage swing 650 800 1200 mv parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 25 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf
ics845252aki revision a september 30, 2009 6 ?2009 integr ated device technology, inc. ICS845252I data sheet femtoclock? crystal-to-cml clock generator ac characteristics table 6a. ac characteristics, v dd = 3.3v5%, t a = -40c to 85c note: electrical parameters are guaranteed ov er the specified ambient operating temperat ure range, which is established when th e device is mounted in a test socket with maintained transverse airflow gr eater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. note 1: f ref = 25 mhz. note 2: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the output diffe rential cross points. note 3: this parameter is defined in accordance with jedec standard 65. note 4: please refer to the phase noise plots. table 6b. ac characteristics, v dd = 2.5v5%, t a = -40c to 85c for notes see table 6a above. symbol parameter test conditio ns minimum typical maximum units f out output frequency; note 1 fbsel = 0, fsel[1:0] = 00 312.5 mhz fbsel = 0, fsel[1:0] = 01 156.25 mhz fbsel = 0, fsel[1:0] = 10 125 mhz fbsel = 0, fsel[1:0] = 11 62.5 mhz fbsel = 1, fsel[1:0] = 00 250 mhz fbsel = 1, fsel[1:0] = 01 125 mhz fbsel = 1, fsel[1:0] = 10 100 mhz fbsel = 1, fsel[1:0] = 11 50 mhz tsk(o) output skew; note 1, 2, 3 60 ps t jit(?) rms phase jitter (random); note 4 fsel = 0, 125mhz, integration range: 1.875mhz ? 20mhz 400 fs fsel = 0, 156.25mhz, integration range: 1.875mhz ? 20mhz 408 fs t r / t f output rise/fall time 20% to 80% 300 850 ps odc output duty cycle fbsel[1:0] 10 48 52 % fbsel[1:0] = 10 46 54 % symbol parameter test conditio ns minimum typical maximum units f out output frequency; note 1 fbsel = 0, fsel[1:0] = 00 312.5 mhz fbsel = 0, fsel[1:0] = 01 156.25 mhz fbsel = 0, fsel[1:0] = 10 125 mhz fbsel = 0, fsel[1:0] = 11 62.5 mhz fbsel = 1, fsel[1:0] = 00 250 mhz fbsel = 1, fsel[1:0] = 01 125 mhz fbsel = 1, fsel[1:0] = 10 100 mhz fbsel = 1, fsel[1:0] = 11 50 mhz tsk(o) output skew; note 1, 2, 3 60 ps t jit(?) rms phase jitter (random); note 4 fsel = 0, 125mhz, integration range: 1.875mhz ? 20mhz 406 fs fsel = 0, 156.25mhz, integration range: 1.875mhz ? 20mhz 441 fs t r / t f output rise/fall time 20% to 80% 300 850 ps odc output duty cycle fbsel[1:0] 10 48 52 % fbsel[1:0] = 10 46 54 %
ics845252aki revision a september 30, 2009 7 ?2009 integr ated device technology, inc. ICS845252I data sheet femtoclock? crystal-to-cml clock generator typical phase noise at 125mhz (3.3v) noise power dbc hz offset frequency (hz)
ics845252aki revision a september 30, 2009 8 ?2009 integr ated device technology, inc. ICS845252I data sheet femtoclock? crystal-to-cml clock generator typical phase noise at 125mhz (2.5v) noise power dbc hz offset frequency (hz)
ics845252aki revision a september 30, 2009 9 ?2009 integr ated device technology, inc. ICS845252I data sheet femtoclock? crystal-to-cml clock generator parameter measurement information 3.3v cml output load ac test circuit rms phase jitter output rise/fall time 2.5v cml output load ac test circuit output skew output duty cycle/pulse width/period scope qx power supply gnd v dd -3.3v 5% cml driver 0v offset frequency f 1 f 2 phase noise plot rms jitter = area under offset frequency markers noise power nq0, nq1 q0, q1 20% 80% 80% 20% t r t f v swing scope qx power supply gnd v dd -2.5v 5% cml driver 0v t sk(o) qx nqx qy nqy t pw t period t pw t period odc = x 100% nq0, nq1 q0, q1
ics845252aki revision a september 30, 2009 10 ?2009 integrated de vice technology, inc. ICS845252I data sheet femtoclock? crystal-to-cml clock generator application information power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is requir ed. the ICS845252I provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd and v dda should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v dd pin and also shows that v dda requires that an additional 10 ? resistor along with a 10 f bypass capacitor be connected to the v dda pin. figure 1. power supply filtering recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pullups and pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. ref_clk input for applications not requiring th e use of the reference clock, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the ref_clk to ground. outputs: cml outputs all unused cml outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. v dd v dda 3.3v or 2.5v 10 ? 10f .01f .01f
ics845252aki revision a september 30, 2009 11 ?2009 integrated de vice technology, inc. ICS845252I data sheet femtoclock? crystal-to-cml clock generator crystal input interface the ICS845252I has been characterized with 18pf parallel resonant crystals. the capacitor values shown in figure 2 below were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. figure 2. crystal input interface lvcmos to xtal interface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configurat ion requires that the output impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will atte nuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . by overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. figure 3. general diagram for lvcmos driver to xtal input interface xtal_in xtal_out x1 18pf parallel crystal c1 27p c2 27p xtal_in xtal_out ro rs zo = ro + rs 50 ? 0.1f r1 r2 v dd v dd
ics845252aki revision a september 30, 2009 12 ?2009 integrated de vice technology, inc. ICS845252I data sheet femtoclock? crystal-to-cml clock generator vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 4. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern fo r the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the groun d plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ? heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz co pper via barrel pl ating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the therma l land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/electrically enhance leadframe base package, amkor technology. figure 4. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ics845252aki revision a september 30, 2009 13 ?2009 integrated de vice technology, inc. ICS845252I data sheet femtoclock? crystal-to-cml clock generator power considerations this section provides information on power dissipation and junction temperature for the ICS845252I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS845252I is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v dd_max * (i dd + i dda ) = 3.465v * (88ma + 12ma) = 346.5mw power (outputs) max = 35.76mw/loaded output pair if all outputs are loaded, the total power is 2 * 35.76mw = 71.52mw total power_ max (3.465v, with all outputs switch ing) = 346.5mw + 71.52mw = 418.02mw 2. junction temperature. junction temperature, tj, is the temperat ure at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. limiting the internal transistor junction temperatur e, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 43.4c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.418w * 43.4c/w = 103c. th is is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ja for 32 lead vfqfn, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 43.4c/w 37.9c/w 34.0c/w
ics845252aki revision a september 30, 2009 14 ?2009 integrated de vice technology, inc. ICS845252I data sheet femtoclock? crystal-to-cml clock generator 3. calculations and equations. the purpose of this section is to calculate the power dissipat ion for the cml driver output pair. the cml output circuit and te rmination are shown in figure 5. figure 5. cml driver (without built-in 50 ? pullup) circuit and termination t o calculate worst case power dissipation into the load, use the following equations: power dissipation when the output driver is logic low: pd_l = i load * v output = (v out_max /r l) * (v dd_max ? v out_max ) = (600mv/50 ? ) * (3.465v ? 600mv) = 34.38mw power dissipation when the output driver is logic high: pd_h = i load * v output = (0.02v/50 ? ) * (3.465v ? 0.02v) = 1.38mw total power dissipation per output pair = pd_h + pd_l = 35.76mw vdd q2 q1 rl1 50 rl2 50 ic q nq i_load v_output
ics845252aki revision a september 30, 2009 15 ?2009 integrated de vice technology, inc. ICS845252I data sheet femtoclock? crystal-to-cml clock generator reliability information table 8. ja vs. air flow table for a 32 vfqfn transistor count the transistor count for the ICS845252I is: 3064 package outline and package dimensions package outline - k suffix for vfqfn packages t able 9. package dimensions reference document: jede c publication 95, mo-220 note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this drawing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 9. ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 43.4c/w 37.9c/w 34.0c/w to p view index area d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref.) n & n even n e d2 2 d2 (ref.) n & n odd 1 2 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or anvil singulation or sawn singulation jedec variation: vhhd-2/-4 all dimensions in millimeters symbol minimum nominal maximum n 32 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.25 0.30 n d & n e 8 d & e 5.00 basic d2 & e2 3.0 3.3 e 0.50 basic l 0.30 0.40 0.50
ics845252aki revision a september 30, 2009 16 ?2009 integrated de vice technology, inc. ICS845252I data sheet femtoclock? crystal-to-cml clock generator table 10. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant part/order number marking package shipping packaging temperature 845252akilf ics45252ail lead-free, 32 lead vfqfn tray -40 c to 85 c 845252akilft ics45252ail lead-free, 32 lead vfqfn 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change an y circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ICS845252I data sheet femtoclock? crystal-to-cml clock generator disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features a nd performance, is subject to change wit hout notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the information contained herein is provided without re presentation or warranty of any kind, whether expr ess or implied, including, but not limited to, the suitability of idt?s products for any particular purpose, an implied warranty of merchantabilit y, or non-infringement of the in tellectual property rights of others . this document is presented only as a guide and does not convey any license under intellectual property ri ghts of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to si gnificantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ris k, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, l ogos and designs, are the property of idt or their respective third party owners. copyright 2009. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056

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